100% OFF/DEAL, IT & SOFTWARE, PAID NOW FREE/UDEMY PROMO CODE

SoC Design 2: Systemverilog Assignment Statements &Synthesis

2 Jul , 2018  

Requirements
  • Know about basics of coding in Systemverilog or Verilog.
  • Be able to write simple Systemverilog Programs
 
Description

This is a short, intermediate level course in Systemverilog HDL from beginning. This will cover only the ONE specific topic in Systemverilog, “the assignment statements”. This is a focused course SoC design engineers, but will be good for verification engineers as well. 

The main objective of this course is to teach the different types of assignment statements in Verilog and Systemverilog, and to map them to the final circuit produced in the IC. This teaches below topics,

  • Continuous assignments
  • Procedural Assignments
  • Blocking Assignment
  • Non Blocking Assignments 

All of them are explained specific to Verilog as well as Systemverilog. Also, the usage of all these statements to produce the basic digital circuits are explained,  which are,

  • Combinational circuits
  • Sequential Circuits
    • Flip Flop
    • Latch

If you are an expert, or someone who is already able to map these statements to the circuits, this course is NOT for you. Also, if you are beginner to Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs.

Who is the target audience?
  • Someone who is already familiar with Systemverilog programming
  • SV programmers confused with blocking and nonblocking of assignments usage
  • SoC Designers looking for knowing circuit produced in the final IC using different types of assignment statements in SV.
 

Best Related Posts


 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Best In Android Development