This is a short, intermediate level course in Systemverilog HDL from beginning. This will cover only the ONE specific topic in Systemverilog, “the assignment statements”. This is a focused course SoC design engineers, but will be good for verification engineers as well.
The main objective of this course is to teach the different types of assignment statements in Verilog and Systemverilog, and to map them to the final circuit produced in the IC. This teaches below topics,
All of them are explained specific to Verilog as well as Systemverilog. Also, the usage of all these statements to produce the basic digital circuits are explained, which are,
If you are an expert, or someone who is already able to map these statements to the circuits, this course is NOT for you. Also, if you are beginner to Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs.